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在锁相环设计中 ,前置双模分频器 (DMP)是一个速度瓶颈 .文中提出一种新的分析方法 ,将限制 DMP速度的因素分为两个方面 ,寄存器级限制 (RL L)和电路级限制 (CL L) .指出影响 DMP速度的原因在 CL L.提出了时钟延迟技术 (CDT)并采用高速触发器 ,解决 CL L 问题 .通过版图提取后仿真显示 ,用这种触发器构成的 0 .8μm n阱CMOS DMP在 5 V下工作频率达到 2 .4GHz
In the PLL design, the front dual-mode divider (DMP) is a speed bottleneck.This paper presents a new analysis method to limit the factors that limit the DMP speed into two aspects, the register-level limit (RL L) And circuit-level limit (CL L). The reasons for the impact on DMP speed are pointed out in CL L. The clock delay technique (CDT) is proposed and high-speed flip-flops are used to solve CL L. The simulation results show that with this flip- The 0 .8μm n-well CMOS DMP is configured to operate at 2.4 V at 5 V