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随着集成电路规模的不断扩大和器件特征尺寸的不断缩减,保持和改善集成电路的制造成品率成为优化电路设计和制造工艺研究的热点.为了减少由冗余物缺陷和丢失物缺陷所引起的成品率损失,选择优先优化的线网成为版图优化过程中的一个重要课题.基于关键面积减小的版图优化是提高集成电路成品率的一种有效途径.本文提出了一种新的短路、开路灵敏度模型,该模型以线网为单位,反映了单位线网上该线网与周围线网间的短路关键面积和自身开路关键面积的大小.由于本文的灵敏度模型是关于单一线网的,同时又包含候选线网周围线网的信息,因此,在优化时可以同时减少候选线网与周围线网之间的短路关键面积以及线网本身的开路关键面积,提高了版图优化的效率.实验结果表明,该灵敏度模型可作为版图优化中线网位置选择的依据.
With the continuous expansion of the scale of integrated circuits and shrinking of device features, maintaining and improving the manufacturing yield of integrated circuits has become a hotspot in the field of circuit design and manufacturing process optimization.In order to reduce the defects caused by redundancy defects and lost objects The loss of yield and the selection of the optimized wire mesh become an important issue in layout optimization.Loading optimization based on the key area reduction is an effective way to improve the yield of integrated circuits.This paper presents a new short circuit, Sensitivity model, which uses the net as a unit, which reflects the key short-circuit area between the net and the surrounding net of the unit net and the size of the key area of the open circuit.Because the sensitivity model of this paper is about a single net, So it can reduce the critical area of short circuit between the candidate line network and the surrounding line network and the key open area of the line network at the same time and improve the efficiency of the layout optimization.Experimental results show that , The sensitivity model can be used as a basis for the layout optimization of the location of the line network.