阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。分析了门控时钟的实现方式,如何借助EDA工具在设计中使用门控时钟,并且附有部分脚本程序,以一个watchdogtimer模块为例,给出了相关的功耗分析报告和优化结果。这样,可以借助EDA工具的帮助,在综合时插入门控时钟,较大幅度地降低功耗,同时附带减小面积,为使用门控时钟进行低功耗设计者提供有益的参考。 Describes how to use the gated clock to design low-power CMOS circuits. The implementation of gated clock is analyzed. How to use the gated clock in the design with EDA tool, and with some script programs, a watchdogtimer module is given as an example, and the related power consumption analysis report and optimization results are given. In this way, with the help of EDA tools, gating clocks can be integrated into synthesis to drastically reduce power consumption with reduced area, providing a useful reference for designers of low-power consumption using gated clocks.