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设计了一种具有前馈结构的Σ-Δ A/D转换器。运用零点、极点优化技术,使Σ-Δ调制器在具有较高稳定性的同时得到优化的信噪比。调制器采用前馈3阶单环结构,采用1位量化,用全差分开关电容方式实现,时钟频率为256 kHz,信号带宽为1 kHz。电路采用SMIC 0.18μmCMOS工艺,仿真结果表明,Σ-Δ A/D转换器达到的信噪比为90.54 dB,有效位数为14.8位;在3.3 V电源电压下,功耗为5.18 mW。
A Σ-Δ A / D converter with feedforward structure is designed. Using zero-point and pole-optimization techniques, the Σ-Δ modulator achieves an optimized signal-to-noise ratio with high stability. The modulator uses a feedforward 3-order single-loop architecture with 1-bit quantization and full differential switched-capacitor implementation with a clock frequency of 256 kHz and a signal bandwidth of 1 kHz. The circuit adopts SMIC 0.18μm CMOS process. The simulation results show that the Σ-Δ A / D converter achieves a signal-to-noise ratio of 90.54 dB and an effective median of 14.8 bits. The power consumption is 5.18 mW at 3.3 V supply voltage.