可测试性设计(Design-For-Testability,简称DFT)是芯片设计的重要环节,它通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑,从而使芯片变得容易测试,大幅度节省芯片测试的成本。文中介绍了在一款通用CPU芯片的设计过程中,为提高芯片的易测性而采取的各种可测试性设计技术,主要包括扫描设计(ScanDesign)、存储器内建自测试(Build-in-self-test,简称BIST)以及与IEEE1149.1标准兼容的边界扫描设计(BoundaryScanDesign,简称BSD)等技术。这些技术的使用为该芯片提供了方便可靠的测试方案。 Design-For-Testability (DFT) is an important part of the chip design. It makes the chip easy to test by inserting various hardware logic used to improve chip testability in the original design of the chip, Significant savings in chip test costs. This paper introduces various testability design techniques to improve the testability of a chip in the design process of a general-purpose CPU chip, including ScanDesign, Build-in- self-test, or BIST for short) and a Boundary Scan Design (BSD) compatible with the IEEE1149.1 standard. The use of these technologies provides a convenient and reliable test solution for the chip.