为适应嵌入式低功耗微处理器的应用，提出了可同时实现浮点乘除法和平方根计算宏模块（ＭＤＳ）的同步串行实现方式．乘法计算采用Ｂｏｏｔｈ算法迭代，除法与平方根计算的实现采用基４　ＳＲＴ算法，在迭代中共用商位查询表，可同步实现部分冗余结果向非冗余二进制的转换．为加快迭代的速度，摒弃了进位传递加法器（ＣＰＡ），而采用进位存储加法器（ＣＳＡ）来实现迭代中的加法运算．宏模块设计控制逻辑简单，资源面积占用少，迭代时间短，经可编程逻辑器件验证，速度可提高１倍以上．在此基础上，提出了对除法和平方根计算异步自定时实现方式的改进方案，该实现方式不仅易于版图布线，而且大大降低了瞬态功耗． In order to adapt to the application of embedded low power microprocessor, a synchronous serial implementation of floating point multiplication and division and square root computing macro block (MDS) is proposed. Multiplication calculation using Booth algorithm iteration, division and square root calculation using the base 4 SRT algorithm, in the iteration shared quotes table can be achieved simultaneously to achieve some of the redundant results to non-redundant binary conversion. In order to speed up the iteration, the carry-through adder (CPA) is eliminated and the carry-save adder (CSA) is used to implement the addition in the iteration. Macro-module design control logic is simple, resource area occupancy less, iteration time is short, verified by programmable logic device, the speed can be increased by 1 times. On this basis, an improved scheme for calculating the asynchronous self-timing implementation of the divide and square root calculation is proposed, which is not only easy to layout layout, but also greatly reduces the transient power consumption.