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为以较小的面积代价实现RSA公钥密码算法及其他一些算法所需的求模、模加、模乘、模幂等运算,该文设计了一种可作为协处理器使用的模运算处理器。运算数据的长度可变,范围从256b到2048b。采用优化的CIOS(coarselyintegratedoperatedscanning)算法以加快模乘的速度。充分的流水线设计使得时钟频率可达60MHz,在该工作频率下完成1024b模幂的时间为57ms。除RAM外的核心电路仅含16000等效门,在0.35μmCMOS工艺条件下,包含RAM的电路总面积仅为3.31mm2。该处理器适合用于嵌入式系统,尤其是面积局限性高的系统。
In order to realize the arithmetic of RSA public-key cryptosystem and some other algorithms such as modulo, modular addition, modulo multiplication and modular exponentiation with a small area cost, this paper designs a modulo operation that can be used as a coprocessor Device. The length of arithmetic data can vary from 256b to 2048b. Adopt optimized CIOS (coarsely integratedly-scaned operating) algorithm to speed up the modular multiplication. Full pipeline design allows the clock frequency up to 60MHz, at this operating frequency to complete 1024b modular exponential time of 57ms. The core circuit except for the RAM contains only 16,000 equivalent gates. Under 0.35μm CMOS process conditions, the total area of the circuit containing RAM is only 3.31mm2. The processor is suitable for use in embedded systems, especially those with high area limitations.