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H.264视频编码标准的去块效应滤波器在改善视频主观质量的同时,也引入了巨大的计算量。为了得到一个高处理能力和低电路规模的去块效应滤波器,提出一种将对外部存储器的读写操作与滤波计算并行执行的滤波算法,并给出了该算法的电路结构。基于0.18μm的工艺,用Verilog语言对该算法和结构进行了实现。结果表明,综合后电路的关键路径最大时延为7 ns,电路规模低于1.65万门,能够以111.7帧/s的帧率对1 280×720分辨率的图像进行滤波处理。与现有的设计相比,本设计节省了32.5%的面积,同时提高了79.3%的处理能力。
H.264 video coding standard deblocking filter to improve the subjective quality of the video at the same time, also introduced a huge amount of computation. In order to get a deblocking filter with high processing power and low circuit size, a filtering algorithm that parallelizes the read and write operation of external memory and filter calculation is proposed, and the circuit structure of the algorithm is given. Based on the 0.18μm process, the algorithm and structure are implemented in Verilog language. The results show that the maximum delay of the critical path of the integrated circuit is 7 ns, and the circuit size is less than 16,500. It can process the 1 280 × 720 resolution image at a frame rate of 111.7 frames / s. Compared with the existing design, the design saves 32.5% area while increasing the processing capacity by 79.3%.