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从改变CMOS电路中能量转换模式的观点出发,研究利用渐变功率时钟的低功耗CMOS电路设计.首先讨论钟控功率信号的代数表示及有关性质,然后归纳采用直流能源的互补CMOS逻辑门转化为采用交流能源的钟控CMOS门电路的设计过程.在此基础上进一步提出采用交流能源的DCVSL电路设计.采用正弦功率时钟的PSPICE模拟证实了钟控DCVSL电路具有正确的逻辑功能及低功耗工作的特点.最后提出了一种将钟控信号转换为标准CMOS逻辑电平的接口电路并用计算机模拟验证了它的有效性.
From the perspective of changing the mode of energy conversion in CMOS circuits, the design of low-power CMOS circuits using a power-of-gradient clock is studied.First, the algebraic representation of clock-controlled power signals and their properties are discussed, and then the complementary CMOS logic gates of DC energy sources are summarized The design process of DC CMOS clock circuit using AC energy is proposed, and DCVSL circuit design based on AC power is further proposed.The PSPICE simulation using sinusoidal power clock confirms that clock DCVSL circuit has the correct logic function and low power consumption Finally, an interface circuit is proposed to convert the clock signal into a standard CMOS logic level and its validity is verified by computer simulation.