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以Altera公司的FPGA芯片EP2C20Q208C8为例,详细介绍了在Quartus II 7.2的环境下,用SOPC Builder构建Nios软核时,自定义FIFO接口元件的方法。通过将采集到的电压信号,在数码管上显示的实验,实现FIFO寄存器与Nios CPU之间的通信。
Taking the FPGA chip EP2C20Q208C8 of Altera Corporation as an example, this article introduces the method of customizing the FIFO interface components when building Nios soft core by using SOPC Builder under Quartus II 7.2 environment. By the acquisition of the voltage signal, digital tube display experiments to achieve the FIFO register and Nios CPU communication.