提出了一种基于Xilinx Virtex-5FPGA的时间数字转换器。利用Virtex-5中专用进位链CARRY4构造的延迟链,对时钟周期进行内插以得到更高精度的测量。此外,运用布局布线约束来减少延迟链的不一致性,降低了微分非线性(DNL)以及积分非线性(INL)。仿真结果表明,最低有效位(LSB)为52.22ps,精度(RMS)约为25ps,INL为0~0.9LSB,DNL为-0.03~0.1LSB。 A time-to-digital converter based on Xilinx Virtex-5 FPGA is proposed. Using the delay chain constructed by CARRY4, a dedicated carry chain in Virtex-5, clock cycles are interpolated for more accurate measurements. In addition, the use of placement and routing constraints to reduce the chain delay inconsistencies, reduced differential nonlinearity (DNL) and integral nonlinearity (INL). The simulation results show that the least significant bit (LSB) is 52.22ps, the accuracy is about 25ps, the INL is 0 ~ 0.9LSB, and the DNL is -0.03 ~ 0.1LSB.