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Abstract: DM642 is a DSP chip specially used for video processing that offered by TI company,it adds a lot of peripheral devices and inter? faces based on C6000 series of chips, with the high speed computing ability,it has a wide range of applications in multimedia field.This pa? per analyzes and describes the works and the main functional modules of two-way video synthesis hardware system based on DM642.
Key words: DM642; video synthesis; functional modules
中图分类号：TP391文献标识码：A文章编号：1009-3044(2012) 06-1400-02
1 Introduction
In recent years, the rapid advances of computer technology and the gradual expansion of market demand,making the application of multi? media get great development,and more and more attention has been paid in the multimedia technology.Video processing technology plays a very important position in various areas of multimedia,and it is widely used in multimedia networks communication,real-time monitoring sys? tem,high-definition digital television and so on.
2 Working principle
As shown in figure 1,the video decoders decode the video signal acquired from the CCD cameras.DM642 control the video decoders’working mode and working state through the I2C bus,and the decoders will decode the video signal into the format that the DM642 can deal with.Then two-way video signal input to DM642 respectively through vp0 and vp1.DM642 will handle the video data.The video data collect? ed by the decoders is stored in SDRAM at first.Because the video data occupies a great space,DM642 cache space can not meet the large amount of data access.So the data would be saved in SDRAM first ,and then DM642 processes the video data.The processed video data would be output to video encoder through vp2[3]. Finally the system transmit the video signal to display device.
Figure 1 Dual video synthesis system principle
3 System structure
The system mainly includes four modules:video capture module,video output module,DSP video processing module and Flash module. Details of each module are as follows: 3.1 Video capture module
Video capture module consists of two CCD cameras and two pieces of video decoder.The video decoder chip is the core of the video cap? ture module.As the efferent signal of CCD camera is analog signal,DM642 can not deal with it directly.Therefore ,we use Philips’9-bit video decoder—SAA7115 to decode the analog signal. SAA7115 is configured as follows: Using 4:2:2 YUV color space signal mechanism;4:2:2 YUV signal is transmitted directly from the IPD[7:0] to the DM642 video port vp0[9:2] pin;PLL drives the clock generator to generate 27MHz clock sync signal LLC. It is output to VP0CLK0.
3.2 DSP video processing module
The establishment of this module divides approximately into 5 parts : the clock, the internal peripheral choice, the initialization of the video port, I2C and the EMIF. The clock part uses 50MHz exterior clock network and the PLL Multiplication factor is 12x, the frequency of the DSP is configured to 600MHz. the basic frequency 6 frequency divisions is the EMIF clock, the SDRAM operating frequency is 100MHz. I2C clock frequency should be between 7~12MHz, and the value is set at 10MHz.Configure the on-chip peripherals by register PERCFG, en? ables the video ports and I2C.The core of video processing module is DM642,DSP works in little endian mode,the boot way is 8-bit ROM
BOOT. Use SCL and SDA of I2C bus for data transmission and the correspondence control,the standard,communication and programmability of I2C can be used. The EMIF part,configure the globle control register to control the clock output,configure control registers of CE0 and CE1 space according to the read-write timing of SDRAM and the FLASH[1]. 3.3 Video output module
The video output module includes the video decoder and the video display device, in which video decoder is the core.The image data processed by DM642 is numeral, the signal is sent from vp2 to MP of SAA7121, separated the Y signal and the Cb, Cr signal by the data man? agement module of the SAA7121 chip; Then the signal is delivered to the internal D/A module to encode it into analog video signal; Finally, the signal is output from CVBS (composite video signal) or Y, C (S is the post signal) pin. The clock signal (LLC) of SAA7121 is 27 MHz, pro? vided by VPOCLK1 of DM642.DM642 configures the the 48 interal registers of SAA7121 chip by I2C interface to control this chip.
3.4 FLASH module
In this system, the FLASH module is mainly used for program storage and the DSP boot loader. Because the AM29LV033C chip has 22 address buses- A[21:0], but the DM642 has 19 address bus only-AEA[22:3], so,DM642 can not traverse all address unit of the FLASH chip. In order to solve this problem, we introduce the CPLD component, FLASH chip pins A[22:19] connects with the CPLD component input/out? put pin, the FLASH memory block 64 sectors should be divided into 8 pages through A[21:19],and each page includes 8 sectors. DM642 real? ize traverse the FLASH chip all address unit through operating the CPLD registers that control A[21:19] [2].
The EMIF load way is to connect DM642 with exteral FLASH by the EMIF interface, video processing procedure is downloaded to FLASH by JTAG interface, when system works, DM642 extracts the procedure from FLASH. But the Bootloader tool on the DM642 piece on? ly can remove 1K code quantity automatically, while procedure quantity in the FLASH may surpass 1K generally. Therefore, we need to pre-store a short procedure in front 1K range of the exteral FLASH, when the bootloader tool remove this program into DM642,and the code begin to run,the code will move the surplus procedure in the FLASH into DM642.This code can be seen as a simple level 2 Bootloader[3].
4 Conclusion
This article mainly introduced the structure, the principle and the blue print of Two-way video synthesis hardware system based on DM642.The system has used special-purpose media processing chip DM642 that developed for multimedia application,enhancing the system performance-to-price ratio.
References:
[1] LIU QIONG,AN TAO,JIN GANG,FU CHENGYU.THE HARDWARE DESIGN OF VIDEO ACQUISITION AND PROCESSING BASED ON DM64[J].COMPUTER INFORMATION,2007(23):180-182.
[2] Wang Zongyue,Liu Jinghui.TMS320DM642 DSP application design and development[M].Beijing:People’s Posts and Telecommunications Press,2009:7-33,103-107.
[3] Guo Weixuan,Guo Baolong.Design and implementation of video processing system based on DM642[J].Electronic Engineering,2009,17(1): 79-81.
Key words: DM642; video synthesis; functional modules
中图分类号：TP391文献标识码：A文章编号：1009-3044(2012) 06-1400-02
1 Introduction
In recent years, the rapid advances of computer technology and the gradual expansion of market demand,making the application of multi? media get great development,and more and more attention has been paid in the multimedia technology.Video processing technology plays a very important position in various areas of multimedia,and it is widely used in multimedia networks communication,real-time monitoring sys? tem,high-definition digital television and so on.
2 Working principle
As shown in figure 1,the video decoders decode the video signal acquired from the CCD cameras.DM642 control the video decoders’working mode and working state through the I2C bus,and the decoders will decode the video signal into the format that the DM642 can deal with.Then two-way video signal input to DM642 respectively through vp0 and vp1.DM642 will handle the video data.The video data collect? ed by the decoders is stored in SDRAM at first.Because the video data occupies a great space,DM642 cache space can not meet the large amount of data access.So the data would be saved in SDRAM first ,and then DM642 processes the video data.The processed video data would be output to video encoder through vp2[3]. Finally the system transmit the video signal to display device.
Figure 1 Dual video synthesis system principle
3 System structure
The system mainly includes four modules:video capture module,video output module,DSP video processing module and Flash module. Details of each module are as follows: 3.1 Video capture module
Video capture module consists of two CCD cameras and two pieces of video decoder.The video decoder chip is the core of the video cap? ture module.As the efferent signal of CCD camera is analog signal,DM642 can not deal with it directly.Therefore ,we use Philips’9-bit video decoder—SAA7115 to decode the analog signal. SAA7115 is configured as follows: Using 4:2:2 YUV color space signal mechanism;4:2:2 YUV signal is transmitted directly from the IPD[7:0] to the DM642 video port vp0[9:2] pin;PLL drives the clock generator to generate 27MHz clock sync signal LLC. It is output to VP0CLK0.
3.2 DSP video processing module
The establishment of this module divides approximately into 5 parts : the clock, the internal peripheral choice, the initialization of the video port, I2C and the EMIF. The clock part uses 50MHz exterior clock network and the PLL Multiplication factor is 12x, the frequency of the DSP is configured to 600MHz. the basic frequency 6 frequency divisions is the EMIF clock, the SDRAM operating frequency is 100MHz. I2C clock frequency should be between 7~12MHz, and the value is set at 10MHz.Configure the on-chip peripherals by register PERCFG, en? ables the video ports and I2C.The core of video processing module is DM642,DSP works in little endian mode,the boot way is 8-bit ROM
BOOT. Use SCL and SDA of I2C bus for data transmission and the correspondence control,the standard,communication and programmability of I2C can be used. The EMIF part,configure the globle control register to control the clock output,configure control registers of CE0 and CE1 space according to the read-write timing of SDRAM and the FLASH[1]. 3.3 Video output module
The video output module includes the video decoder and the video display device, in which video decoder is the core.The image data processed by DM642 is numeral, the signal is sent from vp2 to MP of SAA7121, separated the Y signal and the Cb, Cr signal by the data man? agement module of the SAA7121 chip; Then the signal is delivered to the internal D/A module to encode it into analog video signal; Finally, the signal is output from CVBS (composite video signal) or Y, C (S is the post signal) pin. The clock signal (LLC) of SAA7121 is 27 MHz, pro? vided by VPOCLK1 of DM642.DM642 configures the the 48 interal registers of SAA7121 chip by I2C interface to control this chip.
3.4 FLASH module
In this system, the FLASH module is mainly used for program storage and the DSP boot loader. Because the AM29LV033C chip has 22 address buses- A[21:0], but the DM642 has 19 address bus only-AEA[22:3], so,DM642 can not traverse all address unit of the FLASH chip. In order to solve this problem, we introduce the CPLD component, FLASH chip pins A[22:19] connects with the CPLD component input/out? put pin, the FLASH memory block 64 sectors should be divided into 8 pages through A[21:19],and each page includes 8 sectors. DM642 real? ize traverse the FLASH chip all address unit through operating the CPLD registers that control A[21:19] [2].
The EMIF load way is to connect DM642 with exteral FLASH by the EMIF interface, video processing procedure is downloaded to FLASH by JTAG interface, when system works, DM642 extracts the procedure from FLASH. But the Bootloader tool on the DM642 piece on? ly can remove 1K code quantity automatically, while procedure quantity in the FLASH may surpass 1K generally. Therefore, we need to pre-store a short procedure in front 1K range of the exteral FLASH, when the bootloader tool remove this program into DM642,and the code begin to run,the code will move the surplus procedure in the FLASH into DM642.This code can be seen as a simple level 2 Bootloader[3].
4 Conclusion
This article mainly introduced the structure, the principle and the blue print of Two-way video synthesis hardware system based on DM642.The system has used special-purpose media processing chip DM642 that developed for multimedia application,enhancing the system performance-to-price ratio.
References:
[1] LIU QIONG,AN TAO,JIN GANG,FU CHENGYU.THE HARDWARE DESIGN OF VIDEO ACQUISITION AND PROCESSING BASED ON DM64[J].COMPUTER INFORMATION,2007(23):180-182.
[2] Wang Zongyue,Liu Jinghui.TMS320DM642 DSP application design and development[M].Beijing:People’s Posts and Telecommunications Press,2009:7-33,103-107.
[3] Guo Weixuan,Guo Baolong.Design and implementation of video processing system based on DM642[J].Electronic Engineering,2009,17(1): 79-81.